It is known to form conductor patterns on one or both sides of a number of individual layers of dielectric material, and then to stack and unite such patterned layers to produce a multilayer circuit board. A typical dielectric material used in such multilayer circuit boards is an epoxy-glass material, while the conductor pattern is generally formed from copper, e.g., by selective etching of a thin layer of copper initially covering a layer of the epoxy-glass material or by additive plating. The conductor pattern is comprised of a multitude of fine line paths which terminate on conductive areas called pads or lands. The planes carrying signal lines are called signal planes.
In one method of fabrication of high density multilayer circuit boards, two or more assemblies, called circuitized power cores, as described in U.S. Pat. 4,854,038, which is incorporated herein by reference, comprising two signal planes on either side of one or more power planes are first constructed. Vias are provided for connecting the two signal planes by drilling holes which may range from about 2 mils to about 10 mils in diameter, and an electrically conductive material such as copper is deposited in the vias to make the desired interlayer connection. Drilling is a term used herein to encompass any means for producing a via, including punching and chemical, laser and mechanical hole formation. A multilayer circuit board may be fabricated by stacking and metallurgically bonding two or more circuitized power cores. Reliable electrical connection is required between adjacent vias stacked and bonded in this manner.
In order to provide electrical connections between signal planes, a pad or land of conductive material such as copper is deposited on the outer surface surrounding and in electrical contact with each via. The copper is normally deposited on the pads at the same time as on the fine line paths and in the vias. The lands are stacked, aligned and bonded together with a joining metal, insulation covering signal lines, to form a multilayer structure.
High density packaging configurations comprising small land, via and wiring dimensions will permit fast access to large amounts of data in the next generation of computers, such as in supercomputers. The requirement for high density includes the necessity of increased wiring density and thinner dielectric layers and new materials for the more demanding electrical and mechanical properties required by the high density configurations for enhanced dimensional control.
In the present invention, high density is a term used to describe boards typically made of insulating layers comprising a material having a dielectric constant (Er) of about 4.0 or less, preferably 3.2 to 1.4, at least in the signal line area, in order to provide satisfactorily rapid velocity of signal propagation, reduce unsaturated cross talk, signal noise and attenuation, and still permit the distances between signal planes and power planes to be reduced.
Materials which can be used to provide an Er of 3.2 polytetrafluoroethylene (PTFE), polychlorotri-fluoroethylene (CTFE), and polyperfluoropropylene, and epoxies and cyanates, optionally including filler, such as porous material and certain kinds of quartz or solid or hollow silicon particles, optionally reinforced with fabric such as a mat or woven glass or fluorocarbon fabric. Dielectric materials having an Er between about 3.2 and 1.0 are called high performance dielectric materials, and electrical circuit devices made therewith, especially when the high performance dielectric material is in the signal area, are called high performance circuit devices.
In circuit boards which do not have the stringent dimensional requirements of high density circuit boards, alignment of through holes from layer to layer is made indirectly, using alignment slots and pins. However, in high density circuit boards, the denser circuitry, finer conductor line and track width, thinner dielectric layers, greater number of layers and smaller diameter holes and vias require an absolute, dead-on alignment from layer to layer that is not attainable through means that were satisfactory in the past. In the high density circuitry of the future, through-hole tolerance is such that a small misalignment can mean that there is no electrical interconnection at all, or a highly stressed or high resistance interconnection between the layers where low resistance contact is required. The alignment is thus seen to be a very demanding registration operation. Contributors to alignment problems can include shrinkage of the dielectric material during processing, tooling errors and errors in the artwork used to generate the circuit patterns.
In the past the problems in layer alignment where vias are about 15 mils or less in diameter were noted. In U.S. Pat. 4,566,186 issued Jan. 28, 1986 to Bauer et al, a method is described which includes applying a layer of photoimageable dielectric over a silk screened conductive polymer thick film, which is comprised of a metal dispersed in a polymer. Vias are exposed in the photoimageable dielectric, permitting vias to be as small as about 1 to about 5 mils in diameter. A solder masking step is also included. The techniques and materials described in the '186 patent are quite unlike those of the present invention. The present invention obviates the need for photoimageable dielectric and the associated photolithographic steps.
U.S. Pat. 3,934,335 issued Jan. 27, 1976 to Nelson describes a number of sources of alignment problems and proposed solutions. Unlike the present invention, the '335 patent describes the use of a photoactive dielectric material in a process that seeks to avoid alignment problems and eliminate drilling from layer to layer by applying successive layers of photoactive dielectric, and exposing and developing via openings and circuitry patterns therein.
U.S. Pat. 4,648,179 describes simultaneous bonding at pads of vias filled with bonding metal or alloy, and lamination of polyimide dielectric on a first core to like structures on a second core as a way of avoiding registration problems. The present invention, however, does not require simultaneous lamination of dielectric material and bonding of vias.
However, nowhere in the art is the method or structure of the present invention described, wherein the land areas are placed on a plane separate from the signal planes and perform the dual purpose of easing alignment and enlarging the bond area.
The present invention simplifies alignment, making it possible to provide required faster signal propagation. The present invention, which includes placing larger bonding pads in a plane separate from signal planes, improves via registration from layer to layer, provides greater bonding area, lower stress in the bond between vias, and improves the life and relability of the via-to-via joint.
Accordingly, it is an object of the invention to provide a method and structure wherein vias joining multilayer, high density circuitry are made and aligned through lands located in a plane separate from signal and power planes.
It is a further object of the invention to provide a printed circuit composite having increased contact land areas at which vias are joined and improved interlayer via registration, thereby reducing mechanical stress at the via joint, reducing contamination, and improving the reliability of the via joint after thermal cycling.